The invention relates in general to lateral semiconductor devices including a trench structure, and a method of manufacturing such devices. More specifically, the invention relates to MISFETs with a high breakdown voltage and a low on-resistance, which can be incorporated in integrated circuits, power supplies, motors and other devices.
An example of one type of conventional high voltage lateral MISFETs with low on-resistance characteristics is shown in FIG. 1. A high resistive nxe2x88x92 extended drain 10 is formed in a pxe2x88x92 substrate 8 between a p base region 12 and an n+ drain region 14 to reduce an electric field between a source region 16 and the drain region 14. A gate oxide layer 18 under a gate electrode 20 is thicker at the drain side in order to reduce electric field in the nxe2x88x92 extended drain 10. Generally, lateral MISFETs consist of the following four regions shown in FIG. 1: (1) a source region with a distance of l1, (2) a channel region with a distance of l2, (3) an extended drain region with a distance of l3, and (4) a drain region with a distance of l4. The pitch of the device is the sum of l1+l2,+l3+l4 and determines the packing density of the device and its specific on-resistance. The smaller the pitch, the higher the packing density and the lower the on-resistance per unit area. Present state of the art MISFETs with a breakdown voltage of 80 V require l3 to be 3 xcexcm to reduce the electric field near the drain and prevent premature breakdown. The remaining parameters (l1, l2, and l4) do not influence the breakdown voltage significantly and are required to be 1.5 xcexcm, 2 xcexcm, and 1.5 xcexcm respectively for l1, l2 and l4 (for a 1 xcexcm design rule). Thus, the distance or length of the nxe2x88x92 extended drain 10 is the largest among all of the regions and must be increased as the breakdown voltage of the MISFET increases. As a result, the packing density of the MISFET is sacrificed and on-resistance increases. MISFETS with the above-described structure have already been described. See, for example, T. Efland, et al., xe2x80x9cSelf-Aligned RESURF To LOCOS Region LDMOS Characterization shows Excellent Rsp vs BV Performancexe2x80x9d Proceedings ISPSD""96, pp. 147-150, 1996, the contents of which are incorporated herein by reference.
Results of on-state simulations performed for the structure shown in FIG. 1 with a substrate doping level of 7xc3x971014 cmxe2x88x923, an nxe2x88x92 extended drain surface doping concentration of 7xc3x971017 cmxe2x88x923, and a junction depth of 1.4 xcexcm are illustrated in FIG. 2. For such simulations, the specific on-resistance of the device is estimated to be 1.6 mxcexa9-cm2 for a breakdown voltage of 80 V.
To overcome the packing density limitation discussed above, MISFETs using trench structures have been proposed by N. Fujishima, et al. in U.S. patent application Ser. No. 08/547,910. As illustrated in FIG. 3, a channel 24 and an nxe2x88x92 extended drain 26 are located vertically at a side-wall of a trench formed in a substrate 28. Since the trench MISFET has the nxe2x88x92 extended drain 26 between a source region 31 and a drain region 32, and a thick gate oxide 34 between a gate electrode 36 and the drain region 32, it is possible to optimize the structure to get almost the same current handling capability in the unit cell as the conventional MISFET without reducing the breakdown voltage. The pitch in this case is determined by the sum of l1, l6, and l5, which typically have values of 1.5 xcexcm, 2.0 xcexcm and 0.5 xcexcm respectively (for minimum 1 xcexcm design rules) resulting in half the pitch of the structure in FIG. 1. Therefore, packing density per unit area of the MISFET can be increased and a reduction in on-resistance per unit area achieved.
However, for the device of FIG. 3, two additional masks are needed to define the silicon trench and the drain contact holes. The resulting process also requires strict alignment tolerance among these three masks. In addition, two deep directional etching steps are needed to define the gate and make the drain contact hole inside the initial silicon trench.
In view of the above, it is an object of the present invention to provide a lateral MISFET incorporating a high packing density trench structure and offering high breakdown voltage with low on-resistance and a method of manufacturing the lateral MISFET.
The present invention provides a semiconductor device incorporating a trench structure that combines high breakdown voltage with low on-resistance characteristics and a method for manufacturing the same. In a first embodiment, a Trench Lateral Power MISFET (T-LPM) is provided having a gate and channel regions that are built on the side-wall of the trench. The process used to form the T-LPM uses self-aligned trench bottom contact holes to contact a drain at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a T-LPM with 80 V breakdown voltage having a cell pitch of four microns is disclosed in which an on-resistance of 0.8 mxcexa9-cm2 is realized.
More specifically, a semiconductor device is provided that includes a substrate of a first conductivity type having a trench formed therein that extends from a top surface of the substrate to a defined depth into the substrate. A dielectric material is formed on sidewalls of the trench, wherein a thickness of the dielectric material at the bottom of the trench is greater than a thickness of the dielectric material at the top of the trench. A contact hole extends through the dielectric material at the bottom of the trench to the substrate. A region of a second conductivity type is formed in the substrate beneath the contact hole, and an electrical interconnection material is formed in the trench that extends from the top of the trench through the contact hole to contact the region of second conductivity type.
In the first embodiment a MISFET is provided in which a base region of the first conductivity type is formed near a surface region of the substrate adjacent to the trench, and a source region is formed at the surface of the substrate above the base region. A first conductivity type diffusion region that extends from portions of the lower side walls and bottom of the trench, and a second conductivity type extended drain region is formed in said first conductivity type diffusion region. The region of second conductivity type formed under said contact hole is located in the extended drain region. A gate is located in the trench and is separated from the side walls of the trench and the electrical interconnection material by the dielectric material.
Process steps for forming the first embodiment include:
a) forming a trench in a substrate of first conductivity type;
b) growing a pad oxide in the trench;
c) depositing a nitride layer and etching the nitride layer to leave residual nitride layers that extend from the top of the trench and along the side walls of the trench;
d) extending the depth of the trench into the substrate;
e) depositing a thick oxide layer on the top of the substrate, the portions of the sidewall of the trench not covered by the residual nitride layer and the bottom of the trench;
f) removing the residual nitride layer and pad oxide and forming a gate oxide layer on the portions of the side walls that were previously covered by the residual nitride layer;
g) forming a gate layer on the gate oxide layer;
h) forming an oxide layer over the gate layer;
i) selectively etching the oxide layer formed over the gate layer, the thick oxide layer and the gate layer so that the surface of the substrate is exposed in regions adjacent to the trench and residual films of the gate layer and the thick oxide are left at the side-walls of the trench;
j) forming an oxide layer inside the trench and on the surface of the substrate by a method where oxide growth rate is slower inside the trench than at the surface of the substrate, wherein the thickness of the oxide layer within the trench is less than the thickness of the oxide layer on the surface of the substrate;
k) etching the oxide layer at the bottom of the trench to form a contact hole that extends to the substrate while maintaining a thickness of the oxide layer on the side walls of the trench and a thickness of the oxide layer on the surface of the substrate using a directional etching method; and
l) forming an electrical interconnection material in the trench that extends through the contact hole.
In the preferred method of forming a MISFET device, a first region of the first conductivity type and a second region of a second conductivity type are formed in the substrate through the portions of the sidewall of the trench not covered by the residual nitride layer after step (d) and before step (e). A contact region of second conductivity type in the second region of second conductivity type is formed through the contact hole after step (k) and before step (i). A base of the first conductive type and a source of the second conductive type are formed in the substrate in the exposed regions adjacent to the trench after step (i) and before step (j). The second region of second conductivity type comprises an extended drain region.
In a second embodiment of the invention, a semiconductor device is provided comprising a substrate of a first conductivity type including a trench formed therein that extends from a top surface of the substrate to a defined depth into the substrate. A dielectric material formed on sidewalls of the trench, wherein a thickness of the dielectric material at the bottom of the trench is smaller than a thickness of the dielectric material at the top of the trench. A contact hole extends through the dielectric material at the bottom of the trench to the substrate. A region of a second conductivity type formed in the substrate beneath the contact hole; and an electrical interconnection material formed in the trench that extends from the top of the trench through the contact hole to contact the region of second conductivity type.
In the second embodiment a MISFET is provided in which a drain region of the second conductivity type is formed at the surface of the substrate adjacent to the trench. A first conductivity type diffusion region that extends from the upper portions of the sidewalls, and a second conductivity type extended drain region formed in said first conductivity type diffusion region. A gate located in said trench and separated from the sidewall of the trench and the electrical interconnection material by a dielectric material. A first conductivity type base at the lower portion and bottom of the trench, and a second conductive type source in said base at the lower portion and bottom of the trench. A metal drain electrode is formed on the source region, a metal electrode is formed on the electrical interconnection material and a metal electrode is extended from the gate.
Process steps for forming the second embodiment include:
a) forming a trench in a substrate of first conductive type;
b) forming in it a first region of the first conductivity type and a second region of the second conductivity type into the substrate through portions of the trench;
c) depositing an oxide layer on portions of sidewalls of trench, wherein said oxide layer extends from the top of the trench;
d) forming an extended trench with retaining said oxide layer on the upper portion of said trench sidewall;
e) forming a gate oxide layer on the portion of the sidewalls of said extended trench;
f) forming a gate layer on the gate oxide layer; selectively etching the gate layer, and the gate oxide layer so that the surface of the substrate is exposed in regions adjacent to the trench and residual films of the gate layer and the thick oxide are left on the sidewalls of the trench;
g) forming a base of the first conductivity type and a source of the second conductivity type at the bottom of the trench;
h) forming an oxide layer inside the trench and on the surface of the substrate over the drain by a method where oxide growth rate is slower inside the trench than at the surface of the substrate, wherein the thickness of the oxide layer within the trench is less than the thickness of the oxide layer on the surface of the substrate;
i) etching the oxide layer at the bottom of the trench to form a contact hole that extends to the substrate while maintaining a thickness of the oxide layer on the sidewalls of the trench and surface of the substrate using a directional etching method; and
j) forming an electrical interconnection material in the trench that extends through the contact hole.